This invention relates to integrated circuits (ICs) generally, and to static CMOS (Complementary Metal Oxide Semiconductor) memory cells and logic circuits in particular. The number of circuits that are producible on a substrate of a given size is dependent on the number and size of the elements in each circuit. To reduce the size of such a circuit, many prior art methods redesign the circuit to reduce the number of elements or replace some of the larger circuit elements with smaller ones. For example, one method reduces an eight-transistor memory cell to the six-transistor cell shown in FIG. 1A (see, for example, "Digital Circuits and Logic Design" by S. C. Lee, Prentice-Hall, Englewood Cliffs, N.J., 1976, pages 569-571).
In the memory cell of FIG. 1A, the six transistors act as gates to control the voltages on a pair of nodes 10 and 11. A control transistor 12 controls access from a bit line to node 10, while another control transistor 13 controls access from a bit line to node 11. The memory state of this cell is represented by the voltage on node 10--a "1" is represented by a voltage within a range near a voltage V.sub.1 and a "0" by a voltage within a range near a voltage V.sub.2. Because current leakage across transistor 12 is generally unavoidable, a set of logic transistors 14, 15, 16 and 17 is provided to control access to nodes 10 and 11 from a voltage source 18 of voltage V.sub.1 and a voltage source 19 of voltage V.sub.2. This arrangement maintains the voltage stored on node 10 at its appropriate value. In order to act as a gate controlling access to node 10, each of the transistors 12, 14 and 16 must function to make any preselected path to node 10 have much higher conductance than the other paths. This requires that the on state conductance g.sub.on of each transistor connected to node 10 must be much greater than the off state conductance g.sub.off of the other transistors connected to node 10. Comparable constraints apply to the transistors connected to node 11. In operation, the voltage on node 10 is held within a range near V.sub.1 or V.sub.2 depending on whether the conductance of transistor 14 is respectively much greater or much less than the conductance of transistor 16. Transistor 16 can therefore be replaced with a resistor of conductance g.sub.r in the range: EQU g.sub.off &lt;&lt;g.sub.r &lt;&lt;g.sub.on
without changing the operation of this memory cell. Likewise, transistor 15 or 17 can be replaced with a resistor. (See the article entitled "Resistance-CMOS Circuits" by H. Oguey and E. Vittoz in IEEE Journal of Solid State Circuits, Vol. SC-12, No. 3, June, 1977, page 283.) This procedure provides some design flexibility, but does not reduce the overall number of elements in the circuit.